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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBLTM Architecture
Features

Functional Description
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 are 3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 are equipped with the advanced No Bus Latency (NoBL) logic. NoBLTM is required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133 MHz device). Write operations are controlled by two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. For best practice recommendations, refer to the Cypress application note AN1064 "SRAM System Guidelines".
No Bus LatencyTM (NoBLTM) architecture eliminates dead cycles between write and read cycles Supports up to 133 MHz bus operations with zero wait states Data is transferred on every clock Pin compatible and functionally equivalent to ZBTTM devices Internally self timed output buffer control to eliminate the need to use OE Registered inputs for flow through operation Byte Write capability 3.3V/2.5V IO supply (VDDQ) Fast clock-to-output times 6.5 ns (for 133 MHz device) Clock Enable (CEN) pin to enable clock and suspend operation Synchronous self-timed writes Asynchronous Output Enable (OE) CY7C1471BV33, CY7C1473BV33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-Ball FBGA package. CY7C1475BV33 available in Pb-free and non-Pb-free 209-Ball FBGA package Three Chip Enables (CE1, CE2, CE3) for simple depth expansion Automatic power down feature available using ZZ mode or CE deselect IEEE 1149.1 JTAG Boundary Scan compatible Burst Capability--linear or interleaved burst order Low standby power

Selection Guide
Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 133 MHz 6.5 305 120 117 MHz 8.5 275 120 Unit ns mA mA
Cypress Semiconductor Corporation Document #: 001-15029 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 05, 2008
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Logic Block Diagram - CY7C1471BV33 (2M x 36)
A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER
A1 D1 A0 D0
BURST LOGIC
Q1 A1' A0' Q0
ADV/LD BW A BW B BW C BW D WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
O U T P U T B U F F E R S E
DQs DQP A DQP B DQP C DQP D
OE CE1 CE2 CE3 ZZ
INPUT REGISTER READ LOGIC
E
SLEEP CONTROL
Logic Block Diagram - CY7C1473BV33 (4M x 18)
A0, A1, A MODE CLK C CE ADDRESS REGISTER A1 D1 A0 D0 ADV/LD C WRITE ADDRESS REGISTER A1' Q1 A0' Q0
BURST LOGIC
CEN
ADV/LD BW A BW B WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
O U T P U T B U F F E R S E
DQs DQPA DQPB
WE
OE CE1 CE2 CE3
ZZ
INPUT E REGISTER READ LOGIC
SLEEP CONTROL
Document #: 001-15029 Rev. *B
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Logic Block Diagram - CY7C1475BV33 (1M x 72)
A0, A1, A ADDRESS REGISTER 0
MODE
CLK CEN
C WRITE ADDRESS REGISTER 1
ADV/LD C
A1 A1' D1 Q1 A0 A0' D0 BURST Q0 LOGIC
WRITE ADDRESS REGISTER 2
ADV/LD BW a BW b BW c BW d BW e BW f BW g BW h
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC
WRITE DRIVERS
MEMORY ARRAY
S E N S E A M P S
O U T P U T R E G I S T E R S
D A T A S T E E R I N G
O U T P U T B U F F E R S
E
E
DQ s DQ Pa DQ Pb DQ Pc DQ Pd DQ Pe DQ Pf DQ Pg DQ Ph
WE
INPUT E REGISTER 1
INPUT E REGISTER 0
OE CE1 CE2 CE3
ZZ
READ LOGIC
Sleep Control
Document #: 001-15029 Rev. *B
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Pin Configuration
Figure 1. 100-Pin TQFP Pinout
ADV/LD
BWD
BWC
BWB
BWA
CE1
CE2
CE3
VDD
VSS
CEN
CLK
WE
OE
A 82
A
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
A
BYTE C
BYTE D
DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38
81
A
CY7C1471BV33
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
45 46 47 48 49 50
DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA
BYTE B
BYTE A
39
40
41
42
43
A1
A0
VSS
MODE
VDD
A
A
A
A
44
A
A
NC/144M
A
Document #: 001-15029 Rev. *B
NC/288M
A
A
A
A
A
A
Page 4 of 32
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Pin Configuration (continued)
Figure 2. 100-Pin TQFP Pinout
ADV/LD
BWB
BWA
CE1
CE2
CE3
VDD
VSS
CEN
CLK
WE
OE
NC
NC
A 82
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
A
83
A
NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC
BYTE B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38
81
A
CY7C1473BV33
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
45 46 47 48 49 50
A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC
BYTE A
39
40
41
42
43
A1
A0
VSS
MODE
VDD
A
A
A
A
44
A
A
A
NC/144M
NC/288M
A
Document #: 001-15029 Rev. *B
A
A
A
A
A
Page 5 of 32
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Pin Configuration (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471BV33 (2M x 36)
1 A B C D E F G H J K L M N P R
NC/576M NC/1G DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC/144M MODE
2
A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC A A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
CEN WE
8
ADV/LD OE
9
A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
10
A
11
NC NC DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA NC/288M A
A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
A
A
CY7C1473BV33 (4M x 18)
1 A B C D E F G H J K L M N P R
NC/576M NC/1G NC NC NC NC NC NC DQB DQB DQB DQB DQPB NC/144M MODE
2
A A NC DQB DQB DQB DQB NC NC NC NC NC NC A A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
CEN WE
8
ADV/LD OE
9
A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
10
A
11
A NC DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC NC/288M A
A NC NC NC NC NC NC DQA DQA DQA DQA NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
A
A
Document #: 001-15029 Rev. *B
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Pin Configuration (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1475BV33 (1M x 72)
1 A B C D E F G H J K L M N P R T U V W
DQg DQg DQg DQg DQPg DQc DQc DQc DQc NC DQh DQh DQh DQh DQPd DQd DQd DQd DQd
2
DQg DQg DQg DQg DQPc DQc DQc DQc DQc NC DQh DQh DQh DQh DQPh DQd DQd DQd DQd
3
A BWSc BWSh VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS VDDQ VSS NC/144M A TMS
4
CE2 BWSg
5
A NC
6
ADV/LD WE CE1 OE VDD NC NC NC NC CEN NC NC NC ZZ VDD MODE A A1 A0
7
A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A
8
CE3 BWSb BWSe NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO
9
A BWSf BWSa VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC/288M A TCK
10
DQb DQb DQb DQb DQPf DQf DQf DQf DQf NC DQa DQa DQa DQa DQPa DQe DQe DQe DQe
11
DQb DQb DQb DQb DQPb DQf DQf DQf DQf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe
BWSd NC/576M NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI NC/1G VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC
A
A A
Document #: 001-15029 Rev. *B
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Pin Definitions
Name A0, A1, A BWA, BWB, BWC, BWD, BWE, BWF, BWG, BWH WE ADV/LD IO InputSynchronous InputSynchronous Description Address Inputs used to select one of the Address Locations. Sampled at the rising edge of the CLK. A[1:0] is fed to the two-bit burst counter. Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK.
InputSynchronous InputSynchronous
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input. Advances the on-chip address counter or loads a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After deselection, drive ADV/LD LOW to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select or deselect the device. Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select or deselect the device. Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block inside the device to control the direction of the IO pins. When LOW, the IO pins are enabled to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected. Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. ZZ "Sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition with data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down. Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write sequences, DQPX is controlled by BWX correspondingly. Mode Input. Selects the Burst Order of the Device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. Power Supply Inputs to the Core of the Device.
CLK CE1 CE2 CE3 OE
InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous
CEN
InputSynchronous InputAsynchronous IOSynchronous
ZZ
DQs
DQPX MODE VDD VDDQ VSS
IOSynchronous Input Strap Pin Power Supply
IO Power Supply Power Supply for the IO Circuitry. Ground Ground for the Device.
Document #: 001-15029 Rev. *B
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Pin Definitions (continued)
Name TDO IO JTAG serial output Synchronous Description Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not used, this pin must be left unconnected. This pin is not available on TQFP packages.
TDI
JTAG serial input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. JTAG serial input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAG -Clock Clock Input to the JTAG Circuitry. If the JTAG feature is not used, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die.
TMS
TCK NC
Functional Overview
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 are synchronous flow through burst SRAMs designed specifically to eliminate wait states during write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133 MHz device). Accesses may be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device is latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). Byte Write Select (BWX) can be used to conduct Byte Write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (reads, writes, and deselects) are pipelined. ADV/LD must be driven LOW after the device is deselected to load a new address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied at clock rise:

CEN is asserted LOW CE1, CE2, and CE3 are ALL asserted active WE is deasserted HIGH ADV/LD is asserted LOW
The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133 MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW to drive out the requested data. On the subsequent clock, another operation (read/write/deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, output is tri-stated immediately.
Burst Read Accesses
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 have an on-chip burst counter that enables the user to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW to load a new address into the SRAM, as described in the Single Read Access section. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and wrap around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst sequence.
Document #: 001-15029 Rev. *B
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Single Write Accesses
Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are all asserted active, and (3) WE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The Write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQPX. On the next clock rise the data presented to DQs and DQPX (or a subset for Byte Write operations, see section Truth Table for Read/Write on page 12 for details), input is latched into the device and the write is complete. Additional accesses (read/write/deselect) can be initiated on this cycle. The data written during the write operation is controlled by BWX signals. The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 provide Byte Write capability that is described in the section Truth Table for Read/Write on page 12. The input WE with the selected BWX input selectively writes to only the desired bytes. Bytes not selected during a Byte Write operation remain unaltered. A synchronous self timed write mechanism is provided to simplify the write operations. Byte write capability is included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. Because the CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 are common IO devices, do not drive data into the device when the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQPX inputs. Doing so tri-states the output drivers. As a safety precaution, DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE.
subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. Drive the correct BWX inputs in each cycle of the burst write to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid and the completion of the operation is not guaranteed. The device must be deselected before entering the "sleep" mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00
Linear Burst Address Table
(MODE = GND) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10
Burst Write Accesses
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 have an on-chip burst counter that enables the user to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in section Single Write Accesses on page 10. When ADV/LD is driven HIGH on the
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min Max 120 2tCYC Unit mA ns ns ns ns
Document #: 001-15029 Rev. *B
Page 10 of 32
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows.[1, 2, 3, 4, 5, 6, 7]
Truth Table
Operation Deselect Cycle Deselect Cycle Deselect Cycle Continue Deselect Cycle Read Cycle (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) Write Cycle (Continue Burst) NOP/Write Abort (Begin Burst) Write Abort (Continue Burst) Ignore Clock Edge (Stall) Sleep Mode Address CE CE 1 2 CE3 ZZ Used None None None None External Next External Next External Next None Next Current None H X X X L X L X L X L X X X X X L X H X H X H X H X X X X H X X L X L X L X L X X X L L L L L L L L L L L L L H ADV/LD L L L H L H L H L H L H X X WE X X X X H X H X L X L X X X BWX X X X X X X X X L L H H X X OE X X X X L L H H X X X X X X CEN L L L L L L L L L L L L H X CLK L->H L->H L->H L->H DQ Tri-State Tri-State Tri-State Tri-State
L->H Data Out (Q) L->H Data Out (Q) L->H L->H L->H L->H L->H L->H L->H X Tri-State Tri-State Data In (D) Data In (D) Tri-State Tri-State Tri-State
Notes 1. X = "Don't Care." H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write Selects are asserted, see section Truth Table for Read/Write on page 12 for details. 2. Write is defined by BWX, and WE. See section Truth Table for Read/Write on page 12. 3. When a Write cycle is detected, all IOs are tri-stated, even during Byte Writes. 4. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. CEN = H, inserts wait states. 6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
Document #: 001-15029 Rev. *B
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
The read/write truth table for CY7C1471BV33 follows.[1, 2, 8]
Truth Table for Read/Write
Function Read Write No bytes written Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write Byte C - (DQC and DQPC) Write Byte D - (DQD and DQPD) Write All Bytes The read/write truth table for CY7C1473BV33 follows.[1, 2, 8] WE H L L L L L L BWA X H L H H H L BWB X H H L H H L BWC X H H H L H L BWD X H H H H L L
Truth Table for Read/Write
Function Read Write - No Bytes Written Write Byte a - (DQa and DQPa) Write Byte b - (DQb and DQPb) Write Both Bytes The read/write truth table for CY7C1475BV33 follows.[1, 2, 8] WE H L L L L BWa X H L H L BWb X H H L L
Truth Table for Read/Write
Function Read Write - No Bytes Written Write Byte X - (DQx and DQPx) Write All Bytes WE H L L L BWx X H L All BW = L
Note 8. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active.
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V IO logic levels. The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 contain a TAP controller, instruction register, boundary scan register, bypass register, and ID register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. During power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and enable data to be scanned into and out of the SRAM test circuitry. Only one register is selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. nstruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 16. During power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary `01' pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows the shifting of data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the section Identification Register Definitions on page 19.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO must be left unconnected. During power up, the device comes up in a reset state, which does not interfere with the operation of the device. The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input gives commands to the TAP controller and is sampled on the rising edge of TCK. This ball may be left unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram on page 15. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See the TAP Controller Block Diagram on page 16.) Test Data-Out (TDO) The TDO output ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram on page 15.)
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
TAP Instruction Set
Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in "Identification Codes" on page 19. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail in this section. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which must be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register during power up or whenever the TAP controller is in a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal when in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that because the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state when performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
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TAP Controller State Diagram
1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCA N 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
TAP Controller Block Diagram
0 Bypass Register
210
TDI
Selection Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection Circuitry
TDO
Identification Register
x. . . . .210
Boundary Scan Register
TCK TM S
TAP CONTROLLER
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
3.3V TAP AC Test Conditions
Input pulse levels .................................................VSS to 3.3V Input rise and fall times ................................................... 1 ns Input timing reference levels ...........................................1.5V Output reference levels...................................................1.5V Test load termination supply voltage...............................1.5V
2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 2.5V Input rise and fall time..................................................... 1 ns Input timing reference levels.........................................1.25V Output reference levels.................................................1.25V Test load termination supply voltage.............................1.25V
3.3V TAP AC Output Load Equivalent
1.5V 50 TDO Z O= 50 20pF
2.5V TAP AC Output Load Equivalent
1.25V 50 TDO Z O= 50 20pF
TAP DC Electrical Characteristics and Operating Conditions
(0C < TA < +70C; VDD = 3.3V 0.165V unless otherwise noted)[9] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VIN < VDDQ Test Conditions IOH = -4.0 mA, VDDQ = 3.3V IOH = -1.0 mA, VDDQ = 2.5V IOH = -100 A IOL = 8.0 mA IOL = 1.0 mA IOL = 100 A VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V 2.0 1.7 -0.3 -0.3 -5 Min 2.4 2.0 2.9 2.1 0.4 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.8 0.7 5 Max Unit V V V V V V V V V V V V A
Note 9. All voltages refer to VSS (GND).
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
TAP AC Switching Characteristics
Over the Operating Range[10, 11] Parameter Clock tTCYC tTF tTH tTL Output Times tTDOV tTDOX Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 ns ns ns TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 5 ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time 20 20 50 20 ns MHz ns ns Description Min Max Unit
TAP Timing
Figure 3. TAP Timing
1 Test Clock (TCK )
t TM SS
2
3
4
5
6
t TH t TM SH
t
TL
t CY C
Test M ode Select (TM S)
t TDIS t TDIH
Test Data-In (TDI)
t TDOV t TDOX
Test Data-Out (TDO) DON'T CA RE UNDEFINED
Notes 10.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 11.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Identification Register Definitions
Instruction Field Revision Number (31:29) Device Depth (28:24)
[12]
CY7C1471BV33 CY7C1473BV33 CY7C1475BV33 (2Mx36) (4Mx18) (1Mx72) 000 01011 001001 100100 00000110100 1 000 01011 001001 010100 00000110100 1 000 01011 001001 110100 00000110100 1
Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density Enables unique identification of SRAM vendor Indicates the presence of an ID register
Architecture/Memory Type(23:18) Bus Width/Density(17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0)
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Order - 165FBGA Boundary Scan Order - 209BGA Bit Size (x36) 3 1 32 71 Bit Size (x18) 3 1 32 52 Bit Size (x72) 3 1 32 110
Identification Codes
Instruction EXTEST Code 000 Description Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD
001 010 011 100
RESERVED RESERVED BYPASS
101 110 111
Note 12. Bit #24 is "1" in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
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Boundary Scan Exit Order (2M x 36)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 165-Ball ID C1 D1 E1 D2 E2 F1 G1 F2 G2 J1 K1 L1 J2 M1 N1 K2 L2 M2 R1 R2 Bit # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 165-Ball ID R3 P2 R4 P6 R6 R8 P3 P4 P8 P9 P10 R9 R10 R11 N11 M11 L11 M10 L10 K11 Bit # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 165-Ball ID J11 K10 J10 H11 G11 F11 E11 D10 D11 C11 G10 F10 E10 A9 B9 A10 B10 A8 B8 A7 Bit # 61 62 63 64 65 66 67 68 69 70 71 165-Ball ID B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2
Boundary Scan Exit Order (4M x 18)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 165-Ball ID D2 E2 F2 G2 J1 K1 L1 M1 N1 R1 R2 R3 P2 Bit # 14 15 16 17 18 19 20 21 22 23 24 25 26 165-Ball ID R4 P6 R6 R8 P3 P4 P8 P9 P10 R9 R10 R11 M10 Bit # 27 28 29 30 31 32 33 34 35 36 37 38 39 165-Ball ID L10 K10 J10 H11 G11 F11 E11 D11 C11 A11 A9 B9 A10 Bit # 40 41 42 43 44 45 46 47 48 49 50 51 52 165-Ball ID B10 A8 B8 A7 B7 B6 A6 B5 A4 B3 A3 A2 B2
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Boundary Scan Exit Order (1M x 72)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 209-Ball ID A1 A2 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 L1 L2 M1 M2 N1 N2 P1 P2 R2 R1 Bit # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 209-Ball ID T1 T2 U1 U2 V1 V2 W1 W2 T6 V3 V4 U4 W5 V6 W6 V5 U5 U6 W7 V7 U7 V8 V9 W11 W10 V11 V10 U11 Bit # 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 209-Ball ID U10 T11 T10 R11 R10 P11 P10 N11 N10 M11 M10 L11 L10 P6 J11 J10 H11 H10 G11 G10 F11 F10 E10 E11 D11 D10 C11 C10 Bit # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 209-Ball ID B11 B10 A11 A10 A7 A5 A9 U8 A6 D6 K6 B6 K3 A8 B4 B3 C3 C4 C8 C9 B9 B8 A4 C6 B7 A3
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VDD Relative to GND ........-0.5V to +4.6V Supply Voltage on VDDQ Relative to GND ...... -0.5V to +VDD DC Voltage Applied to Outputs in Tri-State ...........................................-0.5V to VDDQ + 0.5V
DC Input Voltage ................................... -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (MIL-STD-883, Method 3015) Latch Up Current .................................................... >200 mA
Operating Range
Ambient VDD VDDQ Temperature Commercial 0C to +70C 3.3V -5%/+10% 2.5V - 5% to VDD Industrial -40C to +85C Range
Electrical Characteristics
Over the Operating Range[13, 14] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage IO Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Input LOW Voltage[13] Voltage[13] For 3.3V IO For 2.5V IO For 3.3V IO, IOH = -4.0 mA For 2.5V IO, IOH = -1.0 mA For 3.3V IO, IOL = 8.0 mA For 2.5V IO, IOL = 1.0 mA For 3.3V IO For 2.5V IO For 3.3V IO For 2.5V IO Input Leakage Current except ZZ and MODE Input Current of MODE Input Current of ZZ IOZ IDD [15] ISB1 Output Leakage Current VDD Operating Supply Current Automatic CE Power Down Current--TTL Inputs Automatic CE Power Down Current--CMOS Inputs Automatic CE Power Down Current--CMOS Inputs Automatic CE Power Down Current--TTL Inputs GND VI VDDQ Input = VSS Input = VDD Input = VSS Input = VDD GND VI VDD, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX, inputs switching VDD = Max, Device Deselected, VIN 0.3V or VIN > VDD - 0.3V, f = 0, inputs static 7.5 ns cycle, 133 MHz 10 ns cycle, 117 MHz 7.5 ns cycle, 133 MHz 10 ns cycle, 117 MHz All speeds -5 -5 30 5 305 275 200 200 120 2.0 1.7 -0.3 -0.3 -5 -30 5 Test Conditions Min 3.135 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max 3.6 VDD 2.625 Unit V V V V V V V V V V V A A A A A A mA mA mA mA mA
ISB2
ISB3
VDD = Max, Device Deselected, or 7.5 ns cycle, 133 MHz VIN 0.3V or VIN > VDDQ - 0.3V 10 ns cycle, 117 MHz f = fMAX, inputs switching VDD = Max, Device Deselected, VIN VDD - 0.3V or VIN 0.3V, f = 0, inputs static All Speeds
200 200 165
mA mA mA
ISB4
Notes 13. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC) > -2V (pulse width less than tCYC/2). 14. TPower-up: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 15. The operation current is calculated with 50% read cycle and 50% write cycle.
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Capacitance
Tested initially and after any design or process change that may affect these parameters. Parameter CADDRESS CDATA CCTRL CCLK CI/O Description Address Input Capacitance Data Input Capacitance Control Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 100 TQFP Package 6 5 8 6 5 165 FBGA Package 6 5 8 6 5 209 BGA Package 6 5 8 6 5 Unit pF pF pF pF pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, according to EIA/JESD51. 100 TQFP Max 24.63 2.28 165 FBGA Max 16.3 2.1 209 FBGA Max 15.2 1.7 Unit C/W C/W
Figure 4. AC Test Loads and Waveforms 3.3V IO Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 5 pF R = 351 R = 317 ALL INPUT PULSES VDDQ 10% GND 1 ns 90% 90% 10% 1 ns
VL = 1.5V
(a) 2.5V IO Test Load
OUTPUT Z0 = 50 2.5V
INCLUDING JIG AND SCOPE
(b)
(c)
R = 1667 VDDQ 10% 5 pF R = 1538 GND 1 ns ALL INPUT PULSES 90% 90% 10% 1 ns
OUTPUT RL = 50 VL = 1.25V
(a)
INCLUDING JIG AND SCOPE
(b)
(c)
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Switching Characteristics
Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. Test conditions shown in (a) of AC Test Loads and Waveforms on page 23 unless otherwise noted. Parameter tPOWER [16] Clock tCYC tCH tCL tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ tAS tALS tWES tCENS tDS tCES Hold Times tAH tALH tWEH tCENH tDH tCEH Address Hold After CLK Rise ADV/LD Hold After CLK Rise WE, BWX Hold After CLK Rise CEN Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z Clock to High-Z
[17, 18, 19] [17, 18, 19]
Description
133 MHz Min 1 7.5 2.5 2.5 6.5 2.5 3.0 3.8 3.0 0 3.0 1.5 1.5 1.5 1.5 1.5 1.5 0 Max 1
117 MHz Min Max
Unit ms ns ns ns
10 3.0 3.0 8.5 2.5 3.0 4.5 3.8 4.0 1.5 1.5 1.5 1.5 1.5 1.5
Output Times ns ns ns ns ns ns ns ns ns ns ns ns ns
OE LOW to Output Valid OE LOW to Output Low-Z [17, 18, 19] OE HIGH to Output High-Z
[17, 18, 19]
Setup Times Address Setup Before CLK Rise ADV/LD Setup Before CLK Rise WE, BWX Setup Before CLK Rise CEN Setup Before CLK Rise Data Input Setup Before CLK Rise Chip Enable Setup Before CLK Rise
Notes 16. This part has an internal voltage regulator; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation is initiated. 17. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 23. Transition is measured 200 mV from steady-state voltage. 18. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions. 19. This parameter is sampled and not 100% tested.
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Switching Waveforms
Figure 5 shows read-write timing waveform.[20, 21, 22] Figure 5. Read/Write Timing
1 CLK
t CENS t CENH
2
t CYC
3
4
5
6
7
8
9
10
t CH
t CL
CEN
t CES t CEH
CE ADV/LD WE BW X ADDRESS
t AS
A1
t AH
A2
A3
t CDV t CLZ
A4
t DOH Q(A3) Q(A4) t OEHZ t OEV
A5
t CHZ Q(A4+1)
A6
A7
DQ
t DS
D(A1) t DH
D(A2)
D(A2+1)
D(A5)
Q(A6)
D(A7)
OE COM M AND
W RITE D(A1) W RITE D(A2) BURST W RITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1)
t OELZ
t DOH
W RITE D(A5)
READ Q(A6)
W RITE D(A7)
DESELECT
DON'T CARE
UNDEFINED
Notes 20. For this waveform ZZ is tied LOW. 21. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH. 22. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
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Switching Waveforms (continued)
Figure 6 shows NOP, STALL and DESELECT Cycles waveform.
[20, 21, 23]
Figure 6. NOP, STALL, and DESELECT Cycles
1 CLK CEN CE ADV/LD WE BW [A:D] ADDRESS DQ COMMAND
WRITE D(A1)
2
3
4
5
6
7
8
9
10
A1
A2 D(A1)
READ Q(A2) STALL
A3 Q(A2)
READ Q(A3)
A4 Q(A3)
WRITE D(A4) STALL
A5
t CHZ
D(A4)
t DOH NOP READ Q(A5)
Q(A5)
DESELECT CONTINUE DESELECT
DON'T CARE
UNDEFINED
Note 23. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document #: 001-15029 Rev. *B
Page 26 of 32
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Switching Waveforms (continued)
Figure 7 shows ZZ Mode timing waveform.
[24, 25]
Figure 7. ZZ Mode Timing
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes 24. Device must be deselected when entering ZZ mode. See the The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows.[1, 2, 3, 4, 5, 6, 7] on page 11 for all possible signal conditions to deselect the device.
Document #: 001-15029 Rev. *B
Page 27 of 32
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Ordering Information
Not all of the speed, package, and temperature ranges mentioned here are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code CY7C1471BV33-133AXC CY7C1473BV33-133AXC CY7C1471BV33-133BZC CY7C1473BV33-133BZC CY7C1471BV33-133BZXC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1473BV33-133BZXC CY7C1475BV33-133BGC CY7C1475BV33-133BGXC CY7C1471BV33-133AXI CY7C1473BV33-133AXI CY7C1471BV33-133BZI CY7C1473BV33-133BZI CY7C1471BV33-133BZXI CY7C1473BV33-133BZXI CY7C1475BV33-133BGI CY7C1475BV33-133BGXI 117 CY7C1471BV33-117AXC CY7C1473BV33-117AXC CY7C1471BV33-117BZC CY7C1473BV33-117BZC CY7C1471BV33-117BZXC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1473BV33-117BZXC CY7C1475BV33-117BGC CY7C1475BV33-117BGXC CY7C1471BV33-117AXI CY7C1473BV33-117AXI CY7C1471BV33-117BZI CY7C1473BV33-117BZI CY7C1471BV33-117BZXI CY7C1473BV33-117BZXI CY7C1475BV33-117BGI CY7C1475BV33-117BGXI 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-Free 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-Free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-Free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-Free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Document #: 001-15029 Rev. *B
Page 28 of 32
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Package Diagrams
Figure 8. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm)
16.000.20 14.000.10
100 1 81 80
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0-7
R 0.08 MIN. 0.20 MAX.
0.600.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050 *B
A
Document #: 001-15029 Rev. *B
0.10
R 0.08 MIN. 0.20 MAX.
Page 29 of 32
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Package Diagrams
(continued) Figure 9. 165-Ball FBGA (15 x 17 x 1.4 mm)
BOTTOM VIEW TOP VIEW O0.05 M C PIN 1 CORNER O0.25 M C A B
PIN 1 CORNER
O0.450.05(165X)
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
A B
A B
D E F G
1.00
C
C D E F G
17.000.10
H J K
14.00
H J K
M N P R
7.00
L
L M N P R
A 5.00 10.00 0.530.05 0.25 C
+0.05 -0.10
1.00
0.35
0.15 C
B 0.15(4X)
15.000.10
SEATING PLANE C 0.36 1.40 MAX.
51-85165 *A
Document #: 001-15029 Rev. *B
Page 30 of 32
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Package Diagrams
(continued) Figure 10. 209-Ball FBGA (14 x 22 x 1.76 mm)
51-85167 **
Document #: 001-15029 Rev. *B
Page 31 of 32
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33
Document History Page
Document Title: CY7C1471BV33/CY7C1473BV33/CY7C1475BV33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBLTM Architecture Document Number: 001-15029 REV. ** *A *B ECN NO. Issue Date Orig. of Change VKN/KKVTMP New Data Sheet VKN/AESA VKN/PYRS Corrected typo in the "NOP, STALL and DESELECT Cycles" waveform Converted from preliminary to final Added footnote 16 related to IDD Description of Change
1024500 See ECN 1274731 See ECN 2183566 See ECN
(c) Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15029 Rev. *B
Revised March 05, 2008
Page 32 of 32
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
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